Converter from pulse code modulation to delta modulation

ABSTRACT

The system for the conversion of a PCM modulation signal into a Delta M modulation signal comprises: first register means for storing an input signal consisting of m binary digits representing the value x of the quantized signal at the end of a regular PCM modulation sampling period Ti; a &#39;&#39;&#39;&#39;digital integrator&#39;&#39;&#39;&#39; for storing the value e of the quantized signal at the end of sampling period Ti 1; a comparator connected to the first register means and to the digital integrator for comparing the value of the quantized signal x stored in the first register means with the value of the quantized signal e stored in the digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and second register means connected to the comparator for storing said output signal which is representative of the Delta M modulation signal.

United States Patent [191 Deschenes et al.

[ Nov. 13, 1973 [54] CONVERTER FROM PULSE CODE MODULATION TO DELTA MODULATION [75] Inventors: Pierre A. Deschenes, Sherbrooke, Quebec, Canada; Michel Villeret, Gisors, France [73] Assignee: Universite DeSherbrooke,

Sherbrooke, Quebec, Canada [22] Filed: May 22, 1972 [21] Appl. No.: 255,811

Related US. Application Data [62] Division of Ser. No, 44,994, June 10, 1970, Pat. No.

[52] U.S. Cl. 340/347 DD, 179/15 AP, 325/38 B,

Primary Examiner-Thomas J. Sloyan Attorney-Raymond A. Robic [57] ABSTRACT The system for the conversion of a PCM modulation signal into a AM modulation signal comprises: first register means for storing an input signal consisting of m binary digits representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T a digital integrator for storing the value e of the quantized signal at the end of sampling period T a comparator connected to the first register means and to the digital integrator for comparing the value of the quantized signal 1: stored in the first register means with the value of the quantized sig- 332/ nal e stored in the digital integrator and for generating [51] Int. Cl H03k 11/00, H03k 13/24 a positive binary output signal Z if x is larger than 2 [58] Field of Search H03k/13/00; and a negative output signal Z if x is smaller than e;

325/38 /1 5 A /9 332/9 and second register means'connected to the compara- R, 9 T, 11 D; 340/347 DD tor for storing said output signal which is representative of the AM modulation signal. [56] References Cited UNITED STATES PATENTS 10 Claims, 25 Drawing Figures 3,296,612 l/1967 Tomozawa 325/38 B 2,605,361 7/1952 Cutler 325/38 B POWU/V/t 32 34 /36 M/PUT I 2 PCM [XPA/VDER (0MP flAi 1 /?6/5 75R Mir/wow 4 30 z 007 07 AM Ll/VK m n mum/1a nan 3; 772.878

SHEET 3 BF 9 NP)UT REGISTER 5| may REGISTER 0 5| 5 x: 5 H- 5 x4 1 OUTPUT p4 REGISTER 4 Al 9 REGISTER- FIG.4-

t3? I E j 7 E FIG. 49

PATENTEUIIUY 13 I975 3 772 678 SHEET H1! 9 60 NPUT REGISTER on )2 A53 OUTPUT REGIBTER Y3 V4 1 vs FIG.5a

F .5b (INPUT REGISTER o" r 0 ,6 5|

b g n Yo A42 1! \ZP\ Y Y1 A43 X4 1 J7] H 014 V2 A39 9" iL Au. n

h 1 Y5 A45 I M0 016 A Y2 Y5 V" Ya i Y4 7, OUTPUT/ Y: cs OUTPUT Y3 REGISTER RE6\sT n vs P? i a; Y? j 1;; INPUT I INPUT REGISTERF G's-c REflTER F o Yo "M:

F- 015 Y1 A43 A5! Va v4 Y5 j OUTPUT OUTPUT REC IE TER INPUTS F/G.5e bm REEalSTER ANALOG SlGNAL a m m llllullboummmzo sum DOUBLE INTEGRATION) Pmmrenmm 191s 3.772.678

' SHEET 8 0F 9 TO INTEGRATOR TO OUTPUT RE5\5TE.R OF EXPANDER -F'IG 12 FIG. 13

' B07 85 '82v CLOCK F 1\90.1a4 N59 PCM a 7% LINK 1:

,133 M I "z I K DGITAL EXPANDER l DOUBLE INTEGRATOR) SHFT COMPARATOR REL-ASTER CLmK FIG. H

PAIENIEnunv 13 ms 3772.678 sum 9 or 9 CONVERTER FROM PULSE CODE MODULATION TO DELTA MODULATION The present application is a division of US. application Ser. No. 44,994 filed June l0, 1970, now U.S. Pat. No. 3,707,712.

This invention relates to a system permitting the use of delta'modulation (AM) in integrated telecommunication systems and, more particularly, to a digital converter for transfonning pulse code modulation (PCM) signals into AM modulation signals.

As it is commonly known, both the AM and the PCM modulation systems perform a digital transformation of an analog signal. However, the AM modulation possesses two essential characteristics which distinguish such modulation from the PCM modulation. The first characteristic is that a AM system is a closed loop system. The second characteristic is that the information transmitted by a AM modulation system relates to a change of amplitude between two consecutive samples of an analog signal whereas a PCM modulation system transmits the quantized amplitude of each sample of the analog signal.

The encoder of a AM modulation system comprises generally a pulse generator, a modulator, an integrator and a comparator. At the input of the system, the comparator compares the instantaneous amplitude of the analog signal with the amplitude of the analog signal stored in the integrator at the time of the previous sam- I pling and generates a positive or negative output signal depending on whether the instantaneous amplitude of the analog signal is higher or lower than the amplitude of the analog signal stored in the integrator. The output of the comparator controls the output pulses of the pulse generator which are fed to the modulator so that the modulator generates corresponding positive or negative pulses. The train of positive or negative pulses is generated in accordance with the frequency of the pulse generator which frequency is kept constant. The train of positive and negative pulses is also fed to the integrator causing the output of the integrator to rise or fall depending on the polarity of the pulses of the modulator. Two types of integration will be considered here, that is the simple integration and the double integration. In the first case, the output of the integrator consists of the sum of a series of positive or negative quantization steps depending on the positive or negative pulses of the modulator. ln the second case, the output of the integrator is a series of straight line segments the slope of which is modified by each of the above pulses.

In North America, the PCM modulation system has been used for the last few years.,Such system permits the transmissionof 24 communication channels on a single telephone line, each communication channel scriber premises. We would then have a completely digital system right from the subscriber and, with telex in particular, it would be possible to eliminate the hereintofore required separate voice channel since the voice could then be transmitted on the data channel. Such a digital system is not possible using PCM modulation because its cost is so high that it requires the use of one modulator for several subscribers. A second advantage is that the use of a AM modulator would reduce the number of subscriber lines considerably since each subscriber would be allocated a time interval in each frame grouping 24 communication channels, that is 24 subscribers would be connected to two telephone lines.

However, the insertion of AM modulation system in a network where a PCM modulation system is already in use requires that the two systems be compatible so as to permit a subscriber belonging to a AM modulation system to communicate with another subscriber belonging to a PCM modulation system or vice versa.

It is therefore the object of the invention to provide a converter for directly transforming a PCM modulation signal into a AM modulation signal without having to transform the digital signal into an analog form as an intermediate step. The converter for transforming a AM modulation signal into a PCM modulation signal has been disclosed and claimed in parent application Ser. No. 44,994 filed June 10, 1970, now US. Pat. No. 3,707,712.

It is to be noted that in order to be present at the same time on the same network, the AM modulation system and the PCM modulation system must have the same transmission characteristics. As it is already known, a seven digit binary code is used in the PCM modulation system for transmitting analog signals in a coded manner. In addition, the sampling frequency of the PCM modulation system is 8 KHz. Consequently, in the AM modulation system, which uses a single digit binary code, a sampling frequency of 56 KHz must be used in order to beable to generate a number having seven binary digits during a normal PCM sampling period of micro seconds.

The converter, in accordance with the invention, comprises:

a. first register means for storing an input signal consisting of m binary digits and representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T b. a digital integrator for storing the value e of the quantized signal at the time of sampling period T c. a comparator connected to said register means and to said digital integrator for comparing the value of the quantized signal stored in said first register means with the value of the quantized signal stored in said digital integrator and for generating a positive binary output signal Z 1 if x e and a negative binary output signal Z 0 if x e; and

d. second register means connected to said comparator for storing said output signal which is representative of the AM modulation signal.

The invention will be further disclosed with reference to the accompanying drawings which illustrate preferred embodiments of the invention and in which:

FIG. 1 illustrates a block diagram of the transmitter of a AM modulation system;

FIG. 2 illustrates a block diagram of a converter for transforming a PCM modulation signal into a AM modulation signal;

FIG. 3 illustrates a piecewise linear characteristic used for approximating the nonlinear characteristic of a compressor suitable for use in the converter in accordance with the invention wherein the scales are indicated by binary numbers but nevertheless linear;

FIGS. 4a to 4g illustrate circuit diagrams of the compressor;

FIGS. 5a to 5f illustrate circuit diagrams of an expander for performing the reverse operation of the compressor;

FIG. 6, which appears on the same sheet as FIGS. 8 and 9, illustrates a simplified expander in accordance with the invention;

FIG. 7 illustrates a digital integrator used in the converter of the invention;

FIG. 8 illustrates a comparator used in the converter for transforming a PCM modulation signal into a AM modulation signal;

FIG. 9 illustrates a complete converter for transforming a PCM modulation signal into a AM modulation signal including the above-mentioned expander of FIG. 6, integrator of FIG. 7, and comparator of FIG. 8;

FIGS. 10a and 10b illustrate the principle of double integration as compared to simple integration;

FIG. 11 illustrates a converter for transforming a PCM modulation signal into a AM modulation signal in accordance with the second embodiment of the invention;

FIG. 12 illustrates the expander used in the converter of FIG. 11; and

FIG. 13, which appears on the same sheet as FIG. 11, illustrates the comparator used in FIG. 11.

In FIG. 1, there is shown a well known AM transmitter comprising a pulse generator 10 connected to a modulator 12. A comparator 14 compares the instantaneous amplitude of an analog signal applied thereto with the output signal of an integrator 16 in which is stored the amplitude of the analog signal obtained at the time t,., of taking the preceding sample, and generates an output signal the polarity of which corresponds to the difference between the two signals applied to the comparator. Such output signal is applied to modulator l2 and controls the pulses of the pulse generator 10 applied to modulator 12 so that the modulator generates positive or negative pulses depending on the sign of the signal generated by the comparator 14. The train of positive or negative pulses is generated in accordance with the frequency of the pulse generator 10 which is kept constant. The train of positive and negative pulses is also fed to the integrator 16 which is connected in a feed-back loop to the comparator 14 and causes the output of the integrator 16 to rise or fall depending on the polarity of the pulses applied thereto.

The integrator 16 may be of two types: the simple integration type and the double integration type. In the first case, the output of the integrator is the sum of a series of quantization steps which may be positive or negative inaccordance with the pulses of the modulator 12. In the second case, the output of the integrator is a series of straight line segments the slope of which is modified in accordance with the pulses of the modulator. The first embodiment of the invention will disclose a converter for use with an integrator of the simple integration type. The second embodiment of the invention will disclose a converter for use with an integrator of the double integration type.

The following description of the invention will be arranged as follows: 5 l. converter: simple integration a. characteristics b. principles of operation: PCM to AM conversion c. description of PCM to AM converter 0- 1 digital compressor-expander c-2. integrator; c-3. comparator c-4. converter 2. converter: double integration a. characteristics b. description of PCM to AM converter b-l. digital expander b-2. comparator 3. operating time necessary for the conversion 1. converter: simple conversion a. characteristics As commonly known, a signal may only take a definite number of values in quantized systems such as the PCM or AM modulation systems. The voltage gap be tween two successive values is commonly known as a quantization step and will be hereinafter designated by symbol 0-.

In the well known PCM modulation system, the signal is compressed, that is the value of the quantization steps varies depending on the instantaneous amplitude of the analog signal. In other words, the quantization steps are smaller for the weaker signals than for the stronger signals. This is done to improve the transmission of the signal by reducing the deficiencies of the socalled quantizing error which results from the difference between the instantaneous value of the analog signal and the quantized value of the same signal. In the AM modulation system under consideration, the signal does not undergo any dynamic compression which means that a pulse represents an identical increase of the analog signal no matter what the level of such signal In the North American PCM modulation system having 24 channels, a seven binary digit code and a sampling frequency of 8 KI-Iz is used. The normal sampling period T is 125 micro seconds. Consequently, it becomes necessary to register seven single binary digits of each communication of the AM modulation system during such time interval T using a sampling frequency of 56 KHz.

It would be desirable that the equipment used for converting a AM modulation signal into a PCM modulation signal be common to a number of channels. This problem will be studied in chapter 3 of the description. 55 The chapters 1 and 2 disclose the principle of the invention assuming that only one AM channel is to be I converted into one PCM channel or vice-versa.

Various studies have proven that, in the voice band with a sampling frequency of 56 KHz, the ratio between the maximum amplitude A of the signal at the input of a AM modulator and the amplitude of a quantization step should be in the order of ten in order to be able to follow an analog signal of a frequency of 800 Hz. To facilitate the design of the converter, it would be desirable that the ratio K of the value of a AM modulation quantization step over the value of a PCM modulation quantization step before compression be a power of 2. Since the ratio A/rr PCM 1,024, A/o' AM has been chosen to be equal to 8, whereby K (r AM/a PCM 1024/8 2.

The choice of 0* AM A/8 instead of A/ lowers the signal to noise ratio but increases the maximum frequency of the amplitude signal A which may be transmitted without overload distortion. As it is well known, overload distortion occurs when the quantization step is not large enough or the sampling frequency not high enough to permit the integrator output to follow rapid changes in the instantaneous amplitude of the analog signal.

b. principles of operation: PCM to AM conversion FIG. 2 illustrates a block diagram of a PCM to AM converter for transforming the PCM signal into a AM signal at the receiver end of the PCM link. The signal appearing on the PCM link is expanded into an expander 30 from a seven binary digit number into an eleven binary digit number and fed to an input register 32. Such signal is then compared in a comparator 34 with the quantized value PCM stored in memory 36 at the time of the previous sampling period T The output of comparator 34 represents the algebraic increase or decrease of the signal since the previous sampling period and thus one AM value of the modulation signal. Such AM value is stored in an output register 38 and its algebric added to the signal stored in the memory 36; this process of comparison is repeated as many times as required for system compativity (seven times for p. 100) between two sampling PCM periods.

c. description of the PCM to AM converter c-l. digital compressor-expander In the general description of the converter in FIG. 2 of the drawings, a digital expander 30 has been mentioned for converting a seven binary digit number into an eleven binary digit number. Such an expander is disclosed in US. application Ser. No. 26,313 filed Apr. 7, 1970 concerning a compressor-expander. However, a description of such a compressor-expander will be hereinafter disclosed for the purpose of better understanding the present invention.

In telephony, a ratio of 1,000 is generally accepted between the maximum and minimum amplitudes of a signal which may be transmitted by a PCM system. For this reason, the ratio A/a has been chosen to be 1,024 or 2'. Because of the positive and negative amplitudes of the analog signal, there will be 2,048 or 2 quantization steps in a quantized PCM system. However, such a value of a is used for weak signals only and various compression laws wherein 0' depends on the signal level permit to keep the quantizing noise constant and acceptable by using only 2 quantization steps. As it is commonly known, the quantizing noise is caused by the quantizing error resulting from the difference between the instantaneous value of the analog signal and the quantized value of the same signal which is actually transmitted.

F IG. 4 of the accompanying drawings. However, it is to be understood that any other compression law could be used.

It is possible to code the amplitude of an analog signal in two ways:

1. the level varies between 0 and +2A and the quantization steps are numbered 1 to 2 using a number having n binary digits;

2. the level varies between +A and -A and the quantization steps are characterized by a number having n-l binary digits representing the amplitude and an extra binary digit representing the sign or of such amplitude.

The second solution has been retained because it requires less equipment. In FIG. 4 it is only necessary to determine to which group among the six different groups (segments) belongs the binary number and on the other hand, what is its sign. This only requires 6 1 7 identification circuits. On the contrary, the first solution would have required to determine to which group among eleven groups the binary number belongs.

In the Cartesian coordinate system of FIG. 3, the bi nary code shown plotted below the X axis corresponds to analog values which are shown immediately above the X axis. Thus if the binary digits were converted to analog values in a conventional linear digital to analog converter, with 2 l, the resulting analog values would form a first series of linear analog values which are plotted on the X axis. Similarly, a second series of analog values would result from the conversion of the output binary digits in a linear digital to analog converter and this second series of analog values is plotted on the Y axis together with the corresponding digital code. When the first and second series are plotted on the Cartesian coordinate system the resulting series of points define a plurality of straight line segments connected together by breakpoint. These straight line segments, shown in FIG. 3, are an approximation to a logarithmic function such as defined above. In practice the maximum values of x and y are unity so that the values shown on the X and Y axes would be normalized to one.

It is therefore necessary to transform a number x having ten binary digits (the eleventh digit being the sign) into a number y having six binary digits (the seventh digit being the sign). The coordinates of the extremities of the segments are as follows expressed in a system using binary numbers:

O-c-w-.-o COCO-CO OOOOOOO OOOOOOO TABLE 1 Intervals x element from y element from 111 1011 l lll 10111 11111 V1 10000000, 11111111 100000, 101111 V11 100000000, 111111111 110000, 110111 V111 1000000000, 1111111111 111000, 111111 The equations of the eight segments expressed in binary.numbers are as follows:

Equations of Segments Group Group Number Number v11 y=(x/100000)+l0l000 vm y=(x/1000000)+110000 Referring to the above equations, it may be seen that the slopes of the various segments are: 1, 1/10, U100, l/l000, l/l00,000, l/l,000,000.

It is to be noted that the numbers in each group be fore and after transformation consist of one or plural group identification digits and of plural digits Which indicate the level of the number in each group. For example, if the binary digits are numbered 1:, to x in the order of their decreasing weights, a number x in group 11 is composed of seven group identification digits (0000001 and of three digits indicating the level of the number in each group (x x x The transformation of x in this group II is y x/ 10 100 which consists of four group identification digits (y to 0010) and two digits indicating the level in the group. This may be represented by the following equation:

Using the same convention,the transformation in the eight groups will be as follows:

The transfer of a number in each of groups I-Vlll from 10 to six binary elements is illustrated in the following table 2 wherein the 0 have been eliminated.

TABLE 2 Group number IV V Binary element number I VIII The identification logic functions of each of the groups are:

l F o a JB s H a ll 2 0 3 131 53 FIGS. 4a to 4f illustrate electrical diagrams of the transfer circuits required for each group of numbers to effectuate the transformation of Table 2. Such transfer circuits include AND gates A to A and OR gates 0 to 0 An input register 50 and an output register 51 are illustrated for each of the groups for convenience purposes although a single input register 50 and a single output register 51 would be used in practice for all the groups.

Taking the groups separately in consecutive order, it will be seen that a number in group I the identification digits x x x x x x x of which are equal to 0 0 0 0 0 0 0 will permit gate A to conduct to provide a digital output 1 to the first input of gates A A and A to permit such gates to transfer binary digits x x and x stored in the input register 50 of the compressor into the proper storage elements of the output register 51 of the compressor through OR gates 0 to O in accordance with the above-mentioned Table 2. Since only one output register 51 is used in practice, only one set of OR gates 0 to O is needed for all the groups. The output of AND gates A to A is therefore applied to the first input of OR gates O, to 0 v The group identification digits of a number of group II having the form 0 0 0 0 0 0 1 will render gate A, conductive and thereby apply a digital signal 1 to the first input of gates A and A this causing the transfer of binary digits x and x from the input register of the compressor into the proper storage elements y and y of the output register through the second input of OR gates 0 and 0 A number in group 111 having the following identification digits 0 0 0 0 0 1 will render gate A conductive and apply a digital signal 1 to the first input of gates A A and A through OR gate 0 thus causing the transfer of digits x x and x, of the input register of the compressor into the proper storage elements y y and y of the output register thereof through the third input of OR gates 0 to 0 A number in group IV having the following identification digits 0 0 0 0 1 will render gate A conductive and thus apply a digital input 1 to gates A A and A thus causing the transfer of digits x x and x, in the input register of the compressor into the storage elements y and y of the output register. It will be noted that the identification digits of groups 111 and IV are both applied through OR gate 0, to the same transfer gates A,,, A and A Indeed, x x and x must be transferred into storage elements y y, and y in both groups, the only difference being that x, l in group III.

A number in group V having the following identification digits 0 0 0 1 will render gate A conductive and thus apply a digital signal 1 to the first input of gates A to A through OR gate 0 thus transferring digits x x x and x,, in the input register of the compressor into the storage elements y y,, y, and y, of the output register of the compressor.

The output of AND gates A A and A is applied to the register through the fourth input of OR gates O and 0 respectively. 0 0 I will render gate A conductive thus transferring digits x x.,, x: and x into storage elements y y,, y and y It will be noted that the output of gates A and A are both applied through OR gate 0,, to gates A to A This is because the same digits x x x and x are to be transferred into storage elements y y y and y in both groups V and VI except that in group V, ar 1.

An element in group VII having the following identification digits 0 1 will render gate A conductive thus applying a digital signal I to gates A A and A and transferring digits x x and x into the storage elements y y and y, through the fifth input of OR gates 0 to A number in group VIII having the identification digit 1 will apply a digital signal 1 to gates A A and A thus transferring digits x x and x into the storage elements y y, and y FIG. 5g illustrates the storage of the identification digits for each of the groups I to VIII. There is shown an OR gate 0 to which is applied the signals G G and G an OR gate 0 to which is applied the identification signals G G G, and G and OR gate O to which is applied the identification signals G G and G such identification signals being illustrated in FIGS. 5a to 5f. One of the identification signals G, to G becomes equal to 1 when a number pertaining to a predetermined group occurs while the remaining identification signals remain equal to zero. For example, a number in group I causes G alone to be equal to I and, consequently, digits y y and y,, in the storage elements of the output register remain equal to zero.

A number in group II causes a digit 1 to be applied to OR gate 0, to change the state of y into the state 1 while y y and y remain in the state zero.

A number in group III causes a digit y l to be stored in the output register while y, and y remain equal to zero. In addition, a digit 1 is stored in storage element y, by the transfer circuit of FIG. 40.

A number in group IV causes a digit 1 to be applied to OR gate 0 to change the state of y into the state 1 while y and y, remain equal to zero.

A number in group V causes a digit 1 to be applied to OR gate 0 to change the state of y into state 1 while y remains equal to O. In addition, a digit 1 is stored into storage element y by the circuit of FIG. 4d.

An element in group VI causes a signal 1 to be applied to OR gate 0 to change the state of y into state 1 while y remains equal to zero.

An element in group VII causes a digit 1 to be applied to both OR gates O, and 0 thus changing the states of y, and y,, into state 1 while y, remains equal to zero.

An element in group VIII causes a digit 1 to be applied to OR gates 0,, O, and O to change the state of y;,, y and y; into state 1.

The purpose of the digital expander is to transform a signal having seven binary elements back into a signal having eleven binary elements in which 0- is constant for all amplitudes of the signal. The compression law is opposite to that of the compressor, that is if y is the input number having six binary elements, x, the output number, will have 10 binary elements. The equations are as follows:

Group I The transformation method is the same as for the compressor. If the 10 position register is empty before the transfer, the following Table 3 indicates the elements to be placed into it.

TABLES Group number Binary element number 11 III IV V VI VII VIII The identification logic functions of each of the groups are:

l FE 74 7: ll rw 5 74 Y: Y: r-ag Y4 y: y, W F15 Y4 Y3 V 5=ws 4 )a VI y, y 1 ys Y4 )a VI" 8 ys Ya Ya FIGS. 5a to 5f illustrate each of the transfer circuits of the expander including AND gates A to A and OR gates 0 and 0 An input register 60 and an output register 61 are illustrated for each group for convenience purposes only, although a single input register 60 and a single output register 61 would be used in practice for all the groups. As in FIGS. 4a to 4f, OR gates O to 0 located at the input of the register 61 are common to at least two of the FIGS. 5a to 5f.

A number in group I the identification digits y y y of which are 0 0 0 will render gate A conductive and apply a digital signal 1 to AND gates A A and A thus transferring digits y y and y, of the input register 60 of the expander into the storage elements x x, and x, of the'output register 61 of the expander. The output of AND gates A and A is applied to the first input of OR gates 0, and 0 respectively.

An element in group II the identification digits y y y y of which are 0 0 l 0 will render gate A conductive thus applying a digital signal 1 to gates A and A to transfer digits y and y into storage elements x, and x, through the second input of gates O and O A number in group III the identification digits y y y y of which are 0 O l 1 will render gate A conductive thus applying a digital signal 1 to gates A A and A through OR gate O to transfer digits y y and y, into storage elements x,, x, and x The output of AND gates A to A is applied to the output register through the appropriate inputs of OR gates O to 0 An element in group IV the identification digits of which are 0 l 0 will render gate A conductive thus applying a digital signal 1 to gates A A and A and transferring digits y y and y, into storage elements x x and x,,. It is to be noted that the identification of both groups III and IV is performed by the same transfer circuit through OR gate It is because the same digits y y, and y are transferred in both groups except that for group III, y l.

A number in group V having identification digits 0 1 1 will render gate A conductive thus applying a digital signal 1 to gates A to A through OR gate 0 to transfer digits y y y and y into storage elements x x x and 1:, through OR gates 0 to 0 respectively.

An element in group VI having identification digits will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y y and y into storage elements y x x and x It is to be noted that groups V and VI use the same transfer circuit because in both groups the same digits y y y and y are to be transferred into x x x and x except that y l in group V.

An element in group VII having identification digits 1 l 0 will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y and y into storage elements x x and 1:, through the appropriate inputs of OR gates 0 to 0 An element in group VIII having identification digits 1 l I will render gate A conductive thus applying a digital signal 1 to gates A to A and transferring digits y y and y, into storage elements x x, and x through the appropriate inputs of OR gates 0 to 01 The storage of the group identification digits is as follows:

a. a number in group I leaves storage elements x to x, unchanged and thus equal to zero; b. a number in group II stores a digit 1 in storage element x while x to x, remain equal to zero; c. a number in group III stores a digit 1 in storage element x, while leaving storage elements x,, to x equal to zero;

(1. a number in group IV stores a digit l in storage element x while leaving storage elements 1: to x unchanged;

e. a number in group V stores a digit 1 in storage element x while leaving storage elements at, to x,, unchanged;

f. a number in group VI will store a digit 1 in storage element 1:, while leaving storage elements x and x unchanged;

g. a number in group VII will store a digit 1 in x,, while leaving x unchanged;

h. a number in group VIII will store a digit 1 in storage element x,,.

Having described a PCM compressor-expander, it will now be interesting to see how such a compressorexpander may be simplified when applied to a PCM AM modulator in accordance with the invention or vice versa. Indeed, we have seen previously in describing the characteristics of a simple integration converter that K, the multiplication factor of multiplier 24 was 2. Consequently the expander 30 shown schematically in FIG. 5 will also be greatly simplified by the fact that digits x to x are null. Consequently, the above Table 3 will look as follows:

TABLE 4 Group Number Binary Element Number VI VII VIII 8 l y: Y1 9 l y,

The above Table 4 shows that a three digit output register only is required for the expander of FIG. 5. FIG. 6 illustrates that AND gates A A A, A and A and OR gates 0, and 0 only are required from the great number of gates illustrated in FIG. 6. In addition, input register contains only four storage elements and output register 81 contains only three storage elements. The circuit operates as follows:

A number belonging to group VI having identification digits 1 0 is identified by i, 1 and a digit 1 is placed in the storage element x, of the output register through OR gate 0 A number belonging to group VII having identification digits 1 l O is identified by AND gate A which applies a digit 1 to AND gate A thus transferring y into storage element x through OR gate 0 and 1 into storage element x through OR gate 0 A number belonging to group VIII having identification digits 1 1 l is identified by AND gate A which applies a digit 1 to AND gates A and A thus transferring digits y and y into storage elements 2:, and x through OR gates 0, and 0 respectively. In addition, AND gate A stores a digit 1 into storage element x,,. c-2. integrator The block 36 of FIG. 3 may then be a digital integrator such as illustrated in FIG. 9 by reference numeral 90. However, in the system chosen using ten binary digits to represent the amplitude of the signal and one digit to represent the sign, [now reduced to three binary digits (x x x plus one for the sign (1: it becomes necessary to add circuits to distinguish the sign of the amplitude of the signal since the reversible counter can only store the absolute value of the amplitude of the signal. In other words, a predetermined pulse to be applied to the reversible counter must be able to cause the level of the counter to raise or to fall depending on the sign of the signal already stored in it. Therefore, a circuit 91 is provided to detect the passage of the reversible counter through the value zero, this being an indication of a possible change of the sign of the level of the signal stored in the counter. To this effect, an AND gate 90 is connected to the f 1 terminals of storage elements x,,, x and x and provides an output 1 when x x and x-, are all equal to zero. Such output I is applied to a delay device 92 the output of which is applied to two AND gates A and A The polarity of the following digit appearing at the output of AM register 93 will determine which one of gates A and A will conduct to store a digit representative of the sign of the signal in the reversible counter in a memory device 94 which may be a simple flip-flop device. For example, if x A M 1 (positive signal), gate A will conduct to store a digit 1 in storage element x of memory device 94. If on the other hand x A u 0 (negative signal), a signal 1 will be applied from It A M to A to store a digit 1 into Y of memory device 94.

Delay device 92 is used to prevent an early operation of memory device 94 by delaying the opening of gates A and A until after the digit x A M which has brought the level of the reversible counter to 0 has disappeared from the input of gates A and A A second circuit 95 is provided to determine if the absolute value of the level of the counter 90 should rise or fall depending on the sign of the binary digit to be stored in the register and on the sign of the signal already stored in it. Such a circuit comprises two AND gates A and A responsive to flip-flop device 94 and to the signal at the output of register 93. In addition, an OR gate 0,, is connected to the output of AND gates A and A and to the output of delay device 92.

In operation, if x A M and x are both equal to 1, A provides a digital output 1 to the terminal of the reversible counter to increase the level of the signal in the counter. If, on the other hand, x A M 0 and x l, the output of gates A and A will be zero. Such value zero will be inverted by inverter 96 and a digital Signal 1 will be applied to the negative terminal of the counter to lower the level of the signal stored into it.

Let us assume now that the level of the signal in the counter 90 has decreased to a level below zero and that circuit 91 ausedasignal x 0 tobe stored in memory 94. If a signal x AM =0 appears at the output of register 93, gate A94 the inputs of which are responsive to I A M and If will provide a digital signal I to the terminal of the reversible counter to increase the level of the signal stored into the counter. In other words, if a negative signal is already stored into the counter, the appearance of a negative pulse at the output of register 93 will cause the absolute value of the level of the signal in the reversible counter to rise. If, on the other hand, a signal x A M 1 appears at the output of register 93, gates A and A will not conduct and a digital signal 0 will appear at the output of OR gate 0 Such digital signal will be inverted by inverter 96 to a digital signal 1 which is applied to the negative terminal of the reversible counter 90 to decrease the level of the signal already stored in the counter.

The first pulse applied to the reversible counter 90 following the passage of the level of the counter to zero must always be applied to terminal thereof in order to store such pulse in the counter. For this reason, the output s of delay device 92 is also applied to OR gate 0, Indeed, a positive signal x A M 1 following a return of the counter to level zero with x 0 would cause a digital signal 1 to be applied to the terminal of the counter which cannot be done. Similarly, a negative signal x A M 0 when the level of the counter is zero and x 1 would cause a decrease of the level of the counter which is impossible. Therefore, the digital output 1 appearing at the output of the device 92 is applied to the positive terminal of counter 90 to cause the counter to always raise its level by one digit upon reception of the following digit of register 93 after the passage of the counter by the value zero. The above operation of the digital integrator circuit may be summarized by the following logic function:

The above disclosed circuits 91 and 95 of the digital integrator are needed because of the simplification of the compressor. If a number having four binary digits had been chosen to represent the amplitude of a signal varying between 0 and +2A instead of using three binary digits for the amplitude plus a fourth digit for the sign, the compressor would have been much more complex but a reversible counter having four storage elements would have been sufficient without having to provide circuits 91 and 95. It is obvious that in both cases the principle of operation is the same.

c-3. Comparator Proceeding now with the description of the comparator of the PCM to AM converter, the input thereof consists of digits 1:, x x, which represent the amplitude of the signal and of digit x which represents the sign of such amplitude (l for positive signals and 0 for negative signals). The above digits originate from the output of the expander illustrated in FIG. 6 and are stored in a conventional input register (illustrated schematically by reference numeral 32 in FIG. 3 of the drawings) which indicates the level of the signal at instant T The level of the signal at instant T is contained in the storage elements (identified by reference characters e e e e, to distinguish them from the preceding ones) of a digital integrator which may be similar to the digital integrator disclosed in FIG. 9.

In order to generate a AM output signal which corresponds to the original AM signal, it is necessary to compare the PCM, signal (x x x x,) at time T with the signal PCM, at time T and to generate within one period T a signal having seven binary digits which will bring the number e e e e as close as possible to x x x x-,. Such a comparator will provide an output Z 1 when x e and an output Z 0 when x e.

The comparator illustrated in FIG. 11 comprises a first circuit 10 which compares the absolute values of the two signals x and e and its output S is equal to 1 when x x 1:, 0 2,, e e-,. Circuit comprises an arrangement of AND gates A to A OR gates 0, and O and two inverters I and I capable of generating the following logic function:

For example, if the signal x x x is 1 1 1 and signal 2 e e is l l 0, the circuit will operate as follows:

a. the output of AND gate A, will be zero;

b. the output of AND gate A will be equal to zero but inverter I will apply a digital signal 1 to the first input of AND gate A 0. the output of AND gate A will be equal to zero;

d. the output of AND gate A will be equal to zero but such signal will be inverted by inverter I to apply a digit 1 to the first input of AND gate A e. the output of AND gate A will be equal to 1 to open AND gate A and transmit a digital signal 1 through OR gate O to AND gate 116 which is also open and thus will transmit a signal 1 through OR gate 0 to output S of circuit 110. S will consequently be equal to 1 indicating that x e as assumed at the beginning(1ll l10).

A second circuit 111 determines the value Z in function of S, x and e wherein x and e represent the sign of the signals x and e. The following table determines the value 2:

Table 5 OI-OI-QQ 5 Q Q N ---oo---oos ------oooom o--o--oo---N The above Table 5 is satisfied by the following logic function:

Z Sx S Z10 The above function is realized by an arrangement comprising AND gates A and A OR gate O and inverter 1 For example, if x 1, e 0 and S 0, inverter I will transform the signal S 0 into a digital signal 1 applied to the first input of AND gate A Signal E being equal to 1, a digital signal 1 will be applied to OR gate O and Z will be equal to l. The other combinations of S, x and e may be easily verified and are not disclosed in detail. c-4. converter FIG. 12 illustrates a complete PCM to AM converter grouping an expander 120, an integrator 121 and a comparator 122 illustrated in a block diagram form and corresponding to the expander, digital integrator and comparator of FIGS. 6, 7 and 8 respectively. The value of the signal Z is applied to a shift register 123 acting as a buffer and capable of storing seven binary digits representing the AM output signal, and to the reversible counter of the digital integrator disclosed in FIG. 9 of the drawings. It is necessary to memorize the value Z during the above-mentioned operation. For this purpose, such value Z is applied to a memory device 124 which may be a flip-flop. The two reversible portions of the flip-flop 122 are applied to AND gates A and A which are connected to the inputs of AND gates A and A of integrator 121 under the control of a clock. In operation, if Z l, a signal 1 will appear at the output of gate A If Z such signal will be inverted by inverter I and applied to AND gate A through memory device 124. 2. double integration a. characteristics The PCM to AM converter disclosed in the first embodiment of the invention was for use with a AM modulator using an integrator 16 (FIG. 1) performing a simple integration, that is an integrator whose output is a series of quantization steps having equal values and the polarity of which is positive or negative depending on the polarity of the modulator as illustrated in FIG. 10a

' of the drawings. If integrator 16 is of the type performing a double integration wherein the output of the integrator is a series of straight line segments the slope of which is modified by the modulator as illustrated in FIG. 10b, the PCM to AM converter will have to be designed accordingly.

By definition, the quantization step 0' in the case of double integration is the variation of the voltage obtained at the output of a double integrator during a AM sampling period when a pulse is applied thereto from the modulator when the output of such integrator is intially zero. For example, if the double integrator receives a series of pulses ofthe same polarity, the increase of voltage at the end of each AM sampling period will be successively 020-, 30', 4a,

Similarly to the simple integration, it is necessary to define the value of the ratio A/a which permits to follow a predetermined analog signal. It has been found in practice that a ratio A/o' 36 is sufficient, when the integrator is fully discharged (worst condition), to reach in less than one-eighth of a period an analog signal having a slope 2-rrfA when f 1,000 Hz at a sampling rate of 56 KHz. This does not take into effect the quantization noise but ensures that the telecommunication signals will be followed without overloading.

As for the simple integration, it is desirable that the value A/o' be a power of 2 in order to simplify the equipment and such value has been chosen as being 32 or 2 which means that K 0' PCM/0' AM 2 b. description of PCM to AM converter The PCM to AM converter illustrated in FIG. 11 comprises a digital expander 180 connected to a comparator 181 which compares the signal originating from the digital expander with that stored in double integrator 182; block 182 is a digital integrator having two stages of integration, each stage being similar to the integrator of FIG. 7. The output of comparator 181 is applied to shift register 183 through a memory circuit including flip-flop device 184, AND gates A and A and inverter I identical to the one disclosed in the PCM to AM converter with simple integration. The content of the shift register 183 is applied to the AM link under the control of a clock in a known manner. b-l. digital expander The expander used in the PCM to AM converter with double integration is illustrated in FIG. 12 and comprises input register 190, AND gates A to A191, OR gate O and output register 191. Since K 2 groups I, II and III are eliminated and the transformation to be performed is illustrated in the following table:

TABLE 6 Binary Group Number element number IV V VI VII VIII 6 1 y: y: Yo 7 .YF ya yr yo 8 1 Y2 yr 9 1 )2 I0 I The transformation illustrated in Table 8 may be performed as follows:

Taking a number in group IV having the form 0 1.0 y y y digits if, y, y are applied to AND gate A to render such gate conductive and store a digit 1 in storage element x,, of the output register through OR gate 189- A number in group V has the form 0 1 l y y Digits 3 y y applied to AND gate A cause a digit 1 to be applied to the first input of AND gates A and A through OR gate 0 thus causing the transfer of digits y and y into storage elements x and x through OR gates O and O A number in group VI has the form 1 0 y y y y Digits y 3 render AND gate A conductive to again apply a digit l to the first input of AND gates A and A thus transferring digits y and y into storage elements x and x through OR gates O and 0, In addition, the conduction of gate A also stores a digit 1 in storage element x, through OR gate O A number in group VII has the form 1 l 0 y y, y Ditigits y,, y, y render AND gate A conductive to apply a digit 1 to AND gates A A and A thus transferring digits y y and y, into storage elements x x and x through OR gates O O and 0 respectively. In addition it stores a digit I in storage element x through OR gate O A number in group VIII has the form I l l y y y Therefore, digits y y, y applied to AND gate A cause a digit 1 to be applied to AND gates A A and A to transfer y y and y into storage elements x x and x respectively through OR gates O O and 0 In addition, the conduction of gate A stores a digit 1 in storage element x,,.

b 2. comparator The comparator of the PCM to AM converter is illustrated in FIG. 13. As mentioned previously, it must compare the value of the binary element x appearing at the output of the expander 180 with the value of the binary element e stored in the double integrator 182 at time T to find out whether 1: is larger or smaller than e so as to generate a positive or negative pulse correv sponding to the AM modulation signal to be applied to shift register 183. The output Z of the comparator will be 1 when x e and zero when x e.

Similarly to the comparator used in the simple integration, a first circuit is provided to compare the absolute value of the two signals x and e. Its output S is equal to 1 when x x x x x e e e, e e Such a circuit comprises an arrangement of AND gates A to A of OR gates O, to O and of inverters 1 to 1 interconnected in the same fashion as in FIG. 11 to obtain the following logic function:

Taking for example a number x, the significant digits 1, to x of which are 1 l 1 l 1 and a number e the signficant digits e, to e, of which are l 1 l l 0, the above circuit will operate as follows: i

a. AND gate A will remain closed;

b. AND gate A will also remain closed but inverter I, will invert this signal to a digit 1 to be applied to the first input of AND gate A c. AND gate A will remain closed;

(1. AND gate A will remain closed but inverter I will apply a digit 1 to the first input of AND gate A e. AND gate A, will remain closed;

f. AND gate A will also remain closed but inverter I, will invert the output of gate A into a digit 1 to be applied to the first input of AND gate A g. AND gate A will remain closed;

h. AND gate A will also remain closed but inverter I; will invert the output of gate A to a digit 1 applied to the first input of AND gate A i. AND gate A will conduct thus applying digit 1 to the second input of gate A to render such gate conductive. The digit 1 at the output of gate A will be transmitted to AND gates A A and A through OR GATES 0, O O and O This will provide a signal S 1 indicating that in fact, S e as it was assurned at the beginning.

A second circuit determines the value Z in function of S, X and E Such circuit comprises AND gates A and A OR gate O and inverter I which are connected in the same way as the circuit 111 of FIG. 11. Therefore, it appears to be unnecessary to disclose such circuit in detail and reference is made to FIG. 1 for the operation of the circuit.

3. operating time necessary for one conversion The time necessary for one conversion depends on the speed of operation of the logic elements used. To find out such time, it will be necessary to determine the sum of the logic levels to go through and of the multivibrator devices used as storage elements. In the PCM to AM conversion using the simple integration, it may be found that the number of logic levels to go through is 114 and the number of multivibrator elements used is 22. Using MECL II logic elements sold by Motorola Semiconductor Products Incorporated, wherein the propagation time of each logic level is 4 ns and the operation time of each multivibrator is 6 us, the time taken for one PCM to AM conversion would be approximately 600 ns.

The PCM to AM conversion with double integration requires 584 logic levels and 120 multivibrators. With the above logic elements, the progpagation time would be 3.1 micro seconds.

In the PCM system used in North Americ having 24 channels, the time allocated for each channel is 124/24 5.2 micro seconds. In the system used in Europe having 32 channels, the time allocated for each channel is 125/32 3.9 micro seconds. In view of the above, it may be seen that one common circuit may be used for successively converting the different channels.

The principle of the above disclosed converter may also be applied to other types of AM modulation such as for example the continuous AM modulation. It would only be necesaary to replace the first stage of integration used in the double integration by another logic circuit which would be appropriate to the continuous AM modulation. However, the number of pulses to be totalized in the second stage of integration would be much larger. The operating time would then be greatly increased and could exceed the limits of 3.9 or 5.2 micro seconds.

In such a case, other logic circuits which are faster could be used as for example the MECL III logic elements also sold by Motorola Semiconductor Products Incorporated having a propagation time of 1.0 ns. Alternatively, the second stage of integration could be modified. Assuming that it is required to integrate seven positive pulses that is to add binary number 1 1 l to the binary number in the counter. It is possible to effectuate a rapid operation in modifying the reversible counter of the second stage of integration by placing an input on each binary element of the counter, the input x modifying the elements x, to x, but leaving unchanged the elements x to x In other words, the counting is done starting from the element of order i.

For example, to integrate the number 7 it would be necessary to send a pulse to the input x,,, then to the input x, and finally to the input x Consequently, three pulses only are counted instead of seven. The detail of such circuits are not disclosed but the increase of operating speed would result in a more complex reversible counter.

Although the above converter has been disclosed for use with a PCM system having twenty-four channels and a seven digit code, it is to be understood that it could be modified for use with systems having a different number of channels and a different code (for instance 8 bits, p.= 255 or 8 bits A 87.6).

We claim:

1. A system for the conversion of a pulse code modulation signal into a delta modulation signal comprising:

a. an expander for converting a seven or eight binary digit pulse code modulation signal originating from a pulse code modulation link into a m binary digit input signal;

b. first register means connected to the output of said expander for storing said input signal consisting of m binary digits and representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T c. a digital integrator for storing the value e of the quantized signal at the end of sampling period T d. a comparator connected to the outputs of said first register means and of said digital integrator for comparing the value of the quantized signal stored in said first register means with the value of the quantized signal stored in said digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and

e. second register means connected to the output of said comparator for storing the output signal which is representative of the the delta modulation signal.

2. A system as defined in claim 1, for use with a delta modulator of the single integration type, wherein the m-3 less significant digits of said input signal are null thus reducing the number m of significant binary digits in the input signal to three digits representing the amplitude of the signal and one digit representing the sign of said amplitude, said expander comprising an input register having storage elements for storing the amplitude of said pulse code modulation signal, an output register having three storage elements for storing said most significant digits, a first gate circuit responsive to predetermined combinations of binary digits in the input register for identifying the group to which said input signal belongs and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said input register to predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digit relating to the level of the binary digits stored in said input register into the predetermined storage elements of said output register.

3. A system as defined in claim 2, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute values of the amplitude of the signal x stored in the output register of said expander with the amplitude of the signal e stored in said digital integrator and for generating a signal S =1 if x is larger than e and S if x is smaller than e.

4. A system as defined in claim 3, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored into the output register of said expander, to the sign of the signal stored in said digital integrator, and to said signal S for generating said output signal Z.

5. A system as defined in claim 4, further comprising a memory device interconnecting said comparator to said digital integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means.

6. A system as defined in claim 1, for use with a delta modulator of the double integration type, wherein said digital integrator comprises a first stage of integration and a second stage of integration.

7. A system as defined in claim 6, wherein the m-5 less significant digits of said input signal are null thus reducing the number m of significant digits in the input signal to five digits representing the amplitude of the signal and one digit representing the sign of the amplitude, and wherein said expander comprises an input register having storage elements for storing the amplitude of the signal originating from the pulse code modulation link and an output register having five storage elements for storing said five most signficant digits, a first gate circuit responsive to predetermined combination of binary digits in the storage elements of said input register for identifying the group to which said signal belongs and for storing digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of the signal in said input register into the predetermined storage elements of said output register.

8. A system as defined in claim 7, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute value of the amplitude of the signal x stored in the output register of the expander with the amplitude of the signal e stored in the second stage of integration of said digital integrator and for generating a signal S 1 if x is larger than e and S 0 if x is smaller than e.

9. A system as defined in claim 8, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored in the output register of said expander, to the sign of the signal stored in the second stage of integration of said digital integrator, and to said signal S for generating said output signal Z.

10. A system as defined in claim 9, further comprising a memory device interconnecting said comparator to said ditigal integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means. 

1. A system for the conversion of a pulse code modulation signal into a delta modulation signal comprising: a. an expander for converting a seven or eight binary digit pulse code modulation signal originating from a pulse code modulation link into a m binary digit input signal; b. first register means connected to the output of said expander for storing said input signal consisting of m binary digits and representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T1; c. a digital integrator for storing the value e of the quantized signal at the end of sampling period Ti 1 ; d. a comparator connected to the outputs of said first register means and of said digital integrator for comparing the value of the quantized signal stored in said first register means with the value of the quantized sigNal stored in said digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and e. second register means connected to the output of said comparator for storing the output signal which is representative of the the delta modulation signal.
 2. A system as defined in claim 1, for use with a delta modulator of the single integration type, wherein the m-3 less significant digits of said input signal are null thus reducing the number m of significant binary digits in the input signal to three digits representing the amplitude of the signal and one digit representing the sign of said amplitude, said expander comprising an input register having storage elements for storing the amplitude of said pulse code modulation signal, an output register having three storage elements for storing said most significant digits, a first gate circuit responsive to predetermined combinations of binary digits in the input register for identifying the group to which said input signal belongs and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said input register to predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digit relating to the level of the binary digits stored in said input register into the predetermined storage elements of said output register.
 3. A system as defined in claim 2, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute values of the amplitude of the signal x stored in the output register of said expander with the amplitude of the signal e stored in said digital integrator and for generating a signal S 1 if x is larger than e and S 0 if x is smaller than e.
 4. A system as defined in claim 3, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored into the output register of said expander, to the sign of the signal stored in said digital integrator, and to said signal S for generating said output signal Z.
 5. A system as defined in claim 4, further comprising a memory device interconnecting said comparator to said digital integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means.
 6. A system as defined in claim 1, for use with a delta modulator of the double integration type, wherein said digital integrator comprises a first stage of integration and a second stage of integration.
 7. A system as defined in claim 6, wherein the m-5 less significant digits of said input signal are null thus reducing the number m of significant digits in the input signal to five digits representing the amplitude of the signal and one digit representing the sign of the amplitude, and wherein said expander comprises an input register having storage elements for storing the amplitude of the signal originating from the pulse code modulation link and an output register having five storage elements for storing said five most signficant digits, a first gate circuit responsive to predetermined combination of binary digits in the storage elements of said input register for identifying the group to which said signal belongs and for storing digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of the signal in said input register into the predetermined storage elements of said output register.
 8. A system as defined in claim 7, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute value of the amplitude of the signal x stored in the output register of the expander with the amplitude of the signal e stored in the second stage of integration of said digital integrator and for generating a signal S 1 if x is larger than e and S 0 if x is smaller than e.
 9. A system as defined in claim 8, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored in the output register of said expander, to the sign of the signal stored in the second stage of integration of said digital integrator, and to said signal S for generating said output signal Z.
 10. A system as defined in claim 9, further comprising a memory device interconnecting said comparator to said ditigal integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means. 